終於過了第一階段

考了好幾次終於過了，有種安心的感覺，原本還以為要到下一星期才過的了呢！

接下來就利用空閒時間來好好計畫我的期末報告了，期望是別寫到詞窮@@

程式碼研究

always(posedge clk) 代表正緣觸發
parameter 表示參數
wire 為線
[11:0] 表示十二位元
// 表示註解
2'b00中的b代表binary(二進位)
$display 會列出所指定信號的值
quotient 為商
clk為時脈 sysclk則為系統時脈
present_state 表示目前的狀態

乘法機練習

我用4乘5來做練習

利用除法機的程式碼做修改

修改方法:
首先r1要大於0
然後代入r1-1
r2+y
接著指定x=4
y=5
for(x=4; x<=4; x=x+1) 這行是代表X從4開始，到4結束


跑出的結果如下

除法機範例

`define NUM_STATE_BITS 2
`define IDLE 2'b00
`define INIT 2'b01
`define COMPUTE1 2'b10
`define COMPUTE2 2'b11

module cl(clk);
parameter TIME_LIMIT = 110000; //1250;
output clk;
reg clk;

initial
clk = 0;

always
#50 clk = ~clk;

always @(posedge clk)
if ($time > TIME_LIMIT) #70 $stop;

endmodule

module slow_div_system(pb,ready,x,y,r2,sysclk);
input pb,x,y,sysclk;
output ready,r2;
wire pb;
wire [11:0] x,y;
reg ready;
reg [11:0] r1,r2;
reg [`NUM_STATE_BITS-1:0] present_state;

always
begin
@(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x;
ready = 1;
if (pb)
begin
@(posedge sysclk) enter_new_state(`INIT);
r2 <= @(posedge sysclk) 0;
while (r1 >= y)
begin
@(posedge sysclk) enter_new_state(`COMPUTE1);
r1 <= @(posedge sysclk) r1 - y;
@(posedge sysclk) enter_new_state(`COMPUTE2);
r2 <= @(posedge sysclk) r2 + 1;
end
end
end
task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1 ready=0;
end
endtask

always @(posedge sysclk) #20
$display("%d r1=%d r2=%d pb=%b ready=%b", $time, r1,r2, pb, ready);
endmodule

module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;

cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial
begin
pb= 0;
x = 0;
y = 7;
#250;
@(posedge sysclk);
for (x=0; x<=14; x = x+1)
begin
@(posedge sysclk);
pb = 1;
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x/y === quotient)
$display("ok");
else
$display("error x=%d y=%d x/y=%d quotient=%d",x,y,x/y,quotient);
end
$stop;
end
endmodule



雖然結果已經跑出來，但還在研究語法的意義，接下來就嘗試修改成乘法機了

除法機波形圖

這是使用除法機程式碼所跑出來的結果圖

除法機程式碼

module div(r1,r2,r3,pb,clk,x,y,ready) ;

input pb , clk;
input [3:0] x,y;
output [3:0]ready,r3,r2,r1;
wire pb;
wire[3:0] r1,r2,r3;
reg[3:0] r1,r2,r3,ready;
always
begin
@(posedge clk)
r1<=x ;
r2<=0 ;
ready=1;
if (pb) begin while(r1>=1)
begin
@(posedge clk)
r1<=r1-y;
@(posedge clk) r2<=r2+1;
@(posedge clk) r3<=r2;
end
end
end
endmodule

乘法器練習

看到別人有寫出乘法機，所以自己也來練習看看


底下是跑出的波形